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“The importance of analog bandwidth is higher than everything else and is reflected in more and more applications. With the advent of GSPS or RF ADCs, the Nyquist domain has grown 10 times in just a few years, reaching the multi-GHz range. This helps the above applications to further broaden the field of view, but in order to reach the X-band (12 GHz frequency), more bandwidth is still needed. Using a sample-and-hold amplifier (THA) in the signal chain can fundamentally expand the bandwidth to far exceed the ADC sampling bandwidth to meet the needs of demanding and high-bandwidth applications. This article will prove that adding a THA before the latest converters developed for the RF market can achieve bandwidths in excess of 10 GHz.
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Summary
The importance of analog bandwidth is higher than everything else and is reflected in more and more applications. With the advent of GSPS or RF ADCs, the Nyquist domain has grown 10 times in just a few years, reaching the multi-GHz range. This helps the above applications to further broaden the field of view, but in order to reach the X-band (12 GHz frequency), more bandwidth is still needed. Using a sample-and-hold amplifier (THA) in the signal chain can fundamentally expand the bandwidth to far exceed the ADC sampling bandwidth to meet the needs of demanding and high-bandwidth applications. This article will prove that adding a THA before the latest converters developed for the RF market can achieve bandwidths in excess of 10 GHz.
Introduction
GSPS converters are popular at the moment, and their advantages are that they can shorten the RF signal chain and create more resource structures in the FPGA for use, such as reducing the down-conversion of the front-end and the digital down-converter (DDC) of the subsequent stage. However, a considerable number of applications still require high-frequency raw analog bandwidth (BW), which far exceeds the level that RF converters can achieve. In such applications, especially in the defense and instrumentation industries (the same goes for wireless infrastructure), there is still a need to fully extend the bandwidth to 10 GHz or above, and the coverage exceeds the C-band. More and more applications need to be covered. To X band. With the advancement of high-speed ADC technology, people’s demand for high-speed and accurate resolution of ultra-high intermediate frequency (IF) in the GHz region is also increasing, and the baseband Nyquist domain has exceeded 1 GHz and is rising rapidly. This statement may be outdated by the time this article is published, because this aspect is developing very rapidly.
This brings two major challenges: one is the converter design itself, and the other is the front-end design of coupling the signal to the converter, such as amplifier, balun, and PCB design. The better the converter performance, the higher the requirements on the front-end signal quality. More and more applications require the use of high-speed GSPS converters with a resolution of 8 to 14 bits. However, the signal quality of the front end has become a bottleneck-the shortcomings of the system determine the indicators of the entire project.
The broadband defined in this article refers to the use of signal bandwidths greater than hundreds of MHz, and the frequency range is from near DC to 5 GHz-10 GHz. This article will discuss the use of broadband THA or active sampling network, the purpose is to achieve the bandwidth up to infinity (sorry, there is no Toy Story emoji available), and focus on its background theory, which supports the expansion of the RF ADC bandwidth, and The RF ADC alone may not have this capability. Finally, this article will explain some considerations and optimization techniques to help designers realize practical broadband solutions for ultra-wideband applications.
Lay the foundation
For radar, instrumentation and communication applications, high GSPS converters are widely used because it can provide a wider frequency spectrum to expand the system frequency range. However, the wider frequency spectrum poses more challenges to the internal sample-and-hold of the ADC itself, because it is usually not optimized for ultra-wideband operation, and the ADC generally has limited bandwidth, and its high-frequency linearity in these higher analog bandwidth regions /SFDR will drop.
Therefore, using a separate THA in front of the ADC to expand the analog bandwidth has become an ideal solution, so that very high-frequency analog/RF input signals can be sampled at a precise moment. This process implements signal sampling through a low-jitter sampler, and reduces the ADC’s dynamic linearity requirements in a wider bandwidth range, because the sampling rate remains unchanged during the RF analog-to-digital conversion process.
The benefits of this solution are obvious: the analog input bandwidth is fundamentally expanded, the high-frequency linearity is significantly improved, and the high-frequency SNR of the THA-ADC component is improved compared with the performance of the RF ADC alone.
THA characteristics and overview
ADI’s THA series products can provide precise signal sampling in the 18 GHz bandwidth range, with 9 to 10 bit linearity, 1.05 mV noise and noise in the input frequency range from DC to over 10 GHz.
Taking the single-stage THA HMC661 as an example, the generated output consists of two sections. In the sampling mode interval of the output waveform (positive differential clock voltage), the device becomes a unity gain amplifier, and under the constraints of the input bandwidth and output amplifier bandwidth, it copies the input signal to the output stage. During the transition from the positive clock to the negative clock, the device samples the input signal with a very narrow sampling time aperture, and keeps the output at a relatively constant value representing the signal at the sampling time during the negative clock interval. When working with ADCs for front-end sampling, single-stage devices are often preferred (ADI also has a two-stage THA model HMC1061 by Fabry). The reason is that most high-speed ADCs have integrated a THA internally, and their bandwidth is usually much smaller. Therefore, adding a THA before the ADC constitutes a composite two-stage component (or a three-stage component, if a two-stage HMC1061 is used), and the THA is in front of the converter. When using the same technology and design, the linearity and noise performance of a single-stage device is generally better than that of a dual-stage device because the number of stages of a single-stage device is smaller. Therefore, single-stage devices are often the best choice for front-end sampling with high-speed ADCs.
Delay mapping THA and ADC
One of the most difficult tasks in developing the sample-and-hold and ADC signal chain is to set an appropriate timing delay between the moment when the THA captures the sampling event and the moment it should be moved to the ADC to resample the event. The process of setting the ideal time difference between two high-efficiency sampling systems is called delay mapping.
Figure 1. Sample and hold topology: (1a) single row, (1b) double row.
Figure 2. Delay mapping circuit.
Completing this process on the circuit board may be tedious, because the paper analysis may not consider the corresponding delay caused by the propagation interval of the clock traces on the PCB, the delay of the internal component group, the delay of the ADC aperture, and the division of the clock into two different segments The related circuits involved (one clock trace is used for THA and the other clock trace is used for ADC). One way to set the delay between THA and ADC is to use a variable delay line. These devices can be active or passive, and the purpose is to correctly align the time of the THA sampling process and hand it over to the ADC for sampling. This ensures that the ADC samples the stable hold mode part of the THA output waveform to accurately represent the input signal.
As shown in Figure 2, HMC856 can be used to initiate this delay. It is a 5-bit QFN package, 90 ps inherent delay, 3 ps or 25 ps step, 32-bit high-speed delay. Its disadvantage is to set/traverse each delay setting. To enable the new delay setting, every bit/pin on the HMC856 needs to be pulled to a negative voltage. Therefore, it will be a tedious task to find the best delay setting among 32 combinations by soldering pull-down resistors. To solve this problem, ADI uses serially controlled SPST switches and off-board microprocessors to help complete the delay setting faster process.
In order to obtain the best delay setting, apply a signal to the THA and ADC combination, which should be outside the ADC bandwidth. In this example, we select a signal of about 10 GHz and apply a level of -6 dBFS (captured on the FFT Display). The delay setting is now scanned in binary steps, and the signal level and frequency remain constant. Display and capture the FFT during the scanning process, and collect the fundamental power and spurious-free dynamic range (SFDR) values corresponding to each delay setting.
The result is shown in Figure 3a, the fundamental power, SFDR and SNR will vary with each setting applied. As shown in the figure, when the sampling position is placed in a better place (in the process of THA sending the samples to the ADC), the fundamental power will be at the highest level, and the SFDR should be at the best performance (that is, the lowest). Figure 3b is an enlarged view of the delay map scan, the delay set point is 671, that is, the delay should remain fixed at this window/position. Keep in mind that the delay mapping procedure is only valid for the relevant sampling frequency of the system. If the design requires a different sampling clock, it needs to be rescanned. In this example, the sampling frequency is 4 GHz, which is the highest sampling frequency of the THA device used in the signal chain.
Figure 3a. Mapping results of signal amplitude and SFDR performance on each delay setting.
Figure 3b. Mapping results of signal amplitude and SFDR performance for each delay setting (zoomed in).
Front-end design for a large amount of raw analog bandwidth
First of all, if the key goal of the application is to handle a bandwidth of 10 GHz, we obviously should consider the RF approach. Please note that the ADC is still a voltage-type device and does not consider power. In this case, the word “match” should be used with caution. We found that it is almost impossible for a converter front end to match a 100 MSPS converter at every frequency; RF ADCs with high frequency bandwidth will not be much different, but the challenge remains. The term “matching” should refer to the optimization that produces the best results in the front-end design. This is an all-encompassing term, where input impedance, AC performance (SNR/SFDR), signal drive strength or input drive, bandwidth, and passband flatness can all produce the best results for that particular application.
Ultimately, these parameters together define the matching performance of the system application. When starting a broadband front-end design, layout may be the key, and the number of components should be minimized to reduce the loss between two adjacent ICs. In order to achieve the best performance, both aspects are very important. Be careful when connecting analog input networks together. The trace length and matching are the most important, and the number of vias should also be minimized, as shown in Figure 4.
Figure 4. THA and ADC layout.
Figure 5. THA and ADC front-end network and signal chain.
The signal is connected to the THA input in a differential mode (we also provide a reference design link for single-ended RF signal input) to form a single front-end network. In order to minimize the number of vias and the total length, we are particularly careful here so that the vias do not pass through these two analog input paths and help offset any pins in the wiring connection.
The final design is quite simple, just need to pay attention to a few points, as shown in Figure 5. The 0.01 μF capacitor used is a broadband type, which helps to keep the impedance flat over a wide frequency range. Typical finished 0.1 μF capacitors cannot provide a flat impedance response, and usually cause more ripple in the passband flatness response. The 5Ω and 10Ω series resistances between the THA output terminal and the ADC input terminal help reduce the peaking of the THA output and minimize the distortion caused by the residual charge injection of the internal sampling capacitor network of the ADC itself. However, these values need to be chosen carefully, otherwise it will increase signal attenuation and force THA to increase drive strength, or the design may not be able to utilize the full range of the ADC.
Finally, the differential shunt termination is discussed. This is crucial when connecting two or more converters together. Generally, a light load (for example, a 1 kΩ load at the input) helps to maintain linearity and restrain the reverberation frequency. The 120 Ω shunt load of the shunt also has this effect, but it will produce more actual load, in this case 50 Ω, which is exactly the load THA hopes to see and optimize.
Now look at the result! Examining the signal-to-noise ratio or SNR in Figure 6, it can be seen that 8-bit ENOB (effective number of bits) can be achieved in the 15 GHz range. This is pretty good. Think about it for a 13 GHz oscilloscope with the same performance. You might have paid $120,000. As the frequency moves toward the L, S, C, and X bands, the integration bandwidth (ie, noise) and jitter limits begin to become significant, so we see a roll-off in performance.
It should also be noted that in order to keep the level between THA and ADC constant, the ADC’s full-scale input is internally changed to 1.0 V pp through the SPI register. This helps to keep THA in the linear region because its maximum output is 1.0 V pp differential.
Figure 6. SNRFS/SFDR performance results at C6 dBFS.
The linearity result or SFRD is also displayed. Here, the linearity up to 8 GHz exceeds 50 dBc, and the linearity up to 10 GHz exceeds 40 dBc. In order to achieve the best linearity over such a wide frequency range, the design here has been optimized using the AD9689 analog input buffer current setting feature (through the SPI control register).
Figure 7 shows the passband flatness, proving that adding a THA before the RF ADC can achieve a bandwidth of 10 GHz, thereby fully extending the analog bandwidth of the AD9689.
Figure 7. THA and ADC network and signal chain-bandwidth results.
Concluding remarks
For those applications that need to achieve the best performance on multi-GHz analog bandwidth, THA is almost indispensable, at least for now! RF ADC is catching up quickly. It is easy to understand that when sampling a wider bandwidth to cover multiple target frequency bands, the GSPS converter theoretically has the advantage of ease of use, which can eliminate one or more down-mixing stages on the front-end RF band. However, achieving a higher range of bandwidth may present design challenges and maintenance issues.
When using THA in the system, make sure that the location of the sampling point is optimized between THA and ADC. Using the delay mapping procedure described in this article will produce the best overall performance results. Understanding the program is tedious, but very important. Finally, it should be remembered that matching the front end actually means achieving the best performance under a given set of performance requirements of the application. When sampling at X-band frequencies, the Lego-style method (simply connecting 50 Ω impedance modules together) may not be the best method.
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